Patent · US Active

Dynamic code execution location in heterogeneous memory

US10802979B2 · kind B2 · utility

1Cited by

2References

24Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Shu Xu · Shanghai, CN
Tianyou Li · Shanghai, CN
Zidong Jiang · Shanghai, CN
Weiliang Lin · Shanghai, CN
Jinkui Ren · Shanghai, CN
Chaobo Zhu · Shanghai, CN
Xiaokang Qin · Shanghai, CN

Key dates

Filing date	Jan 27, 2017
Grant date	Oct 13, 2020
Priority date	—
Expiry date	Jan 27, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F17/11
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.