Hybrid analog-digital matrix processors
US10803259B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2020 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Feb 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.