Method for forming a low-k spacer
US10804373B2 · kind B2 · utility
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2References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Jul 22, 2019 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Jul 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure is directed to formation of a low-k spacer. For example, the present disclosure includes an exemplary method of forming the low-k spacer. The method includes depositing the low-k spacer and subsequently treating the low-k spacer with a plasma and/or a thermal anneal. The low-k spacer can be deposited on a structure protruding from the substrate. The plasma and/or thermal anneal treatment on the low-k spacer can reduce the etch rates of the spacer so that the spacer is etched less in subsequent etching or cleaning processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.