Clock and data recovery devices with fractional-N PLL
US10804913B1 · kind B1 · utility
4Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.