Method and apparatus for performing layout designs using stem cells
US10808333B2 · kind B2 · utility
16Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Jan 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for designing an integrated circuit layout are disclosed. In one embodiment, the method includes generating a stem cell library with stem cell layouts, wherein each stem cell layout includes an analog core area where a device element resides, and abutment boundaries on left, right, top, and bottom sides of the analog core area. The method also includes mapping device elements in a schematic netlist to the stem cell layouts in the stem cell library. In addition, the method includes placing and routing the mapped device elements to optimize a layout for the schematic netlist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.