Mapping software constructs to synchronous digital circuits that do not deadlock
US10810343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Jan 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A language disclosed herein includes a loop construct that maps to a circuit implementation. The circuit implementation may be used to design or program a synchronous digital circuit. The circuit implementation includes a hardware pipeline that implements a body of a loop and a condition associated with the loop. The circuit implementation also includes the hardware first-in-first-out (FIFO) queues that marshal threads (i.e. collections of local variables) into, around, and out of the hardware pipeline. A pipeline policy circuit limits a number of threads allowed within the hardware pipeline to a capacity of the hardware FIFO queues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.