Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization
US10810345B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Apr 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method modifies a manufacturing process for integrated circuits that include memory chips and a memory buffer. One or more processors identify a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits. The processor(s) identify a location and address of each memory chip in the identified failed integrated circuits that has a memory chip failure. The processor(s) identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed such that a manufacturing process for the integrated circuits is modified based on the FA pareto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.