Patent · US Active

Battery life based on inhibited memory refreshes

US10811076B1 · kind B1 · utility

1Cited by

2References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ramkumar Jayaraman · Kanchinakote, IN
Krishnaprasad H · Bengaluru, IN
Kausik Ghosh · Kanchinakote, IN

Key dates

Filing date	Jun 29, 2019
Grant date	Oct 20, 2020
Priority date	—
Expiry date	Jun 29, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C5/148
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.