Refresh control circuit, memory device including the same and method of operating the same for hammer refresh operation
US10811077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2018 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Dec 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device a plurality of memory banks, a hammer address manager, and a refresh controller. The hammer address manager manages access addresses with respect to the plurality of memory banks and provides a hammer address for a hammer refresh operation among the access addresses, the hammer address being the access address that is accessed more than other access addresses. The refresh controller generates a hammer refresh address signal based on the hammer address, the hammer refresh address signal corresponding to a row that is physically adjacent to a row corresponding to the hammer address such that the row physically adjacent to the row corresponding to the hammer address is refreshed by the hammer refresh operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.