Patent · US Active

SRAM architecture

US10811084B2 · kind B2 · utility

0Cited by

4References

19Claims

0Family size

Assignee

XENERGIC AB · SE

Inventors

Babak Mohammadi · Lund, SE
Joachim Neves Rodrigues · Lund, SE

Key dates

Filing date	Apr 5, 2019
Grant date	Oct 20, 2020
Priority date	—
Expiry date	Apr 5, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.