Data reading method, low voltage detection logic circuit, integrated circuit and chip
US10811106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2017 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Oct 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data reading method, a low voltage detection logic circuit, an integrated circuit and a chip are provided. The data reading method includes that: under the condition that a request for reading data from a NonVolatile Memory (NVM) is received, a pre-burnt region return value is read from a preset pre-burnt region of the NVM (S101); whether the pre-burnt region return value is equal to a target pre-burnt value or not is determined (S102); and under the condition that the pre-burnt region return value is equal to the target pre-burnt value, a first control signal is generated, and the first control signal is sent to an NVM controller and the first control signal is used for controlling the VNM controller to read the data from the NVM (S103).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.