Memory device and microelectronic package having the same
US10811402B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2018 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Dec 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a memory device and microelectronic package having the same. The microelectronic package comprises at least one memory device which is adapted to be stacked vertically with one another, and a processing device stacked vertically and adjacently with the at least one memory device and electrically connected to the conductive interconnects. Each of the memory devices comprises a substrate and a plurality of memory units. The substrate presents a front surface and a back surface. The memory units are formed on the front surface, each of which comprises a plurality of memory cells and a plurality of conductive interconnects electrically connected to the memory cells. In each of the memory units, the conductive interconnects contribute to a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.