Gate electrode having upper and lower capping patterns
US10811505B2 · kind B2 · utility
0Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2018 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | May 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.