Patent · US Active

Semiconductor device and method for manufacturing same

US10811520B2 · kind B2 · utility

0Cited by
4References
20Claims
0Family size

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Key dates

Filing dateJul 3, 2018
Grant dateOct 20, 2020
Priority date
Expiry dateJul 3, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/661

Abstract

A method for manufacturing a semiconductor device, includes: forming a well region (201) in a semiconductor substrate (200) and forming a channel region (202) in the well region (201), and forming a gate oxide layer (210) and a polysilicon layer (220) on the well region (201); etching a portion of the gate oxide layer (210) and the polysilicon layer (220), and exposing a first opening (221) used for forming a source region and a second opening (223) used for forming a drain region; forming a first dielectric layer (230) and a second dielectric layer (240) on the polysilicon layer (220) and in the first opening (221) and the second opening (223) successively, and forming a source region side wall at a side surface of the first opening (221) and forming a drain region side wall at a side surface of the second opening (223); forming a dielectric oxide layer (250) on the polysilicon layer (220), etching the dielectric oxide layer and retaining the dielectric oxide layer (250) located on the drain region side wall; removing the second dielectric layer (240) in the source region side wall and retaining the first dielectric layer (230) therein.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.