Reduced number of counters for reliable messaging
US10812416B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2017 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | May 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/1097
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A shared memory maintained by sender processes stores a sequence number counter per destination process. A sender process increments the sequence number counter in the shared memory in sending a message to a destination process. The sender process sends a data packet comprising the message and at least a sequence number specified by the sequence number counter. All of the sender processes share a sequence number counter per destination process, each of the sender processes incrementing the sequence number counter in sending a respective message. Receiver processes run on the hardware processor, each of the receiver processes maintaining a local memory counter on the memory, the local memory counter associated with a sending node. The local memory counter stores a sequence number of a message received from the sending node. The receiver process delivers incoming data packets ordered by sequence numbers of the data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.