Merging techniques in data compression accelerator of a data processing unit
US10812630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2018 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Jan 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes a hardware-based programmable data compression accelerator for the data processing unit including a pipeline for performing string substitution. The disclosed string substitution pipeline, referred to herein as a “search block,” is configured to perform string search and replacement functions to compress an input data stream. In some examples, the search block is a part of a compression process performed by the data compression accelerator. The search block may support single and multi-thread processing, and multiple levels of compression effort. In order to achieve high-throughput, the search block processes multiple input bytes per clock cycle per thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.