Reduced and pipelined hardware architecture for Montgomery Modular Multiplication
US10817262B2 · kind B2 · utility
32Cited by
47References
18Claims
0Family size
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Key dates
| Filing date | Nov 8, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Apr 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/728
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware implementations of Montgomery modular multiplication are described. The number of components as well as the number of cycles may be reduced by using a lookup table and multiplexer for selecting terms to be added during calculations. Also a loop unrolling technique may be used improve performance. A chain of pipeline adder modules and a chain of delay and shift modules may be used to pipeline calculations of multiple sets of operands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.