Combined instruction for addition and checking of terminals
US10817288B2 · kind B2 · utility
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7Claims
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Key dates
| Filing date | Jan 19, 2017 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Jun 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/073
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core comprising in its set of instructions, a combined addition and bound-checking instruction (ADDCK) defining an integer n implicitly, or explicitly as a parameter of the instruction; an adder having a width p strictly greater than n bits; and a processing circuit (MUX, 42) designed to respond to the combined instruction by activating an overflow signal (BX) when the adder generates a carry of rank n during the addition of operands of width p.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.