Optimizing software-directed instruction replication for GPU error detection
US10817289B2 · kind B2 · utility
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Key dates
| Filing date | Oct 3, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Jan 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Software-only and software-hardware optimizations to reduce the overhead of intra-thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.