Input/output translation lookaside buffer (IOTLB) quality of service (QoS)
US10817447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2016 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Feb 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure may be related to an electronic device that includes a root complex; and a processor coupled with the root complex. The root complex may identify a first direct memory access (DMA) transaction and a second DMA transaction respectively related to a first task and a second task of a device communicatively coupled with the root complex through an input/output (I/O) fabric. The root complex may further cache a first memory translation related to the first DMA transaction in a first micro translation lookaside buffer (uTLB) of the root complex. The root complex may further cache a second memory translation related to the second DMA transaction in a second uTLB of the root complex. Other embodiments may be described and/or claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.