Dynamic lane access switching between PCIe root spaces

US10817454B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Chih-Cheh Chen · Hillsboro, US
• Janusz Jurski · Hillsboro, US
• Amit Kumar Srivastava · San Jose, US
• Malay Trivedi · Chandler, US
• James Mitchell · Waterloo, US
• Piotr Kwidzinski · Folsom, US
• David N. Lombard · Rossmoor, US

Key dates

• Filing date: Apr 26, 2019
• Grant date: Oct 27, 2020
• Expiry date: Apr 26, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/1028
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.