System and method of designing integrated circuit by considering local layout effect
US10817637B2 · kind B2 · utility
0Cited by
16References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2017 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Aug 16, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.