Scan signal line driving circuit and display device including same
US10818260B2 · kind B2 · utility
0Cited by
1References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 14, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Nov 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each unit circuit includes a thin film transistor (first stabilization transistor) having a gate terminal to which a clear signal which goes to an on level when a frame period ends applied, a drain terminal connected to a charge holding node, and a source terminal to which a potential of an off level is applied. Here, a gate length of the thin film transistor is set to be larger than gate lengths of other charge holding node turn-off transistors. Alternatively, a multi-gate structure is adopted for the thin film transistor and a single gate structure is adopted for the other charge holding node turn-off transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.