Semiconductor memory device for preventing occurrence of row hammer issue
US10818337B2 · kind B2 · utility
4Cited by
2References
39Claims
0Family size
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Key dates
| Filing date | Aug 2, 2017 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Dec 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.