Semiconductor memory device for supporting operation of neural network and operating method of semiconductor memory device
US10818347B2 · kind B2 · utility
1Cited by
7References
18Claims
0Family size
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Key dates
| Filing date | May 24, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | May 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.