Resistive memory devices having address-dependent parasitic resistance compensation during programming
US10818352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | May 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.