Semiconductor device and method of manufacturing the same
US10818601B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2020 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Jun 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/386
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.