Three-dimensional semiconductor memory device with vertical structures penetrating a dummy insulating pattern in a connection region
US10818687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | May 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.