Array substrate, preparation method thereof and display panel
US10818694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Oct 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/131
Abstract
The present disclosure relates to array substrate, preparation method thereof and display panel. An array substrate comprises: a first thin film transistor and a second thin film transistor over a substrate; wherein the first thin film transistor comprises a first portion of a first insulating layer, the first insulating layer comprises a first recess corresponding to the second thin film transistor, and the second thin film transistor is located in the first recess; and wherein a thickness of a second portion of the first insulating layer, which is below the bottom of the first recess, is smaller than that of the first portion of the first insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.