Method for manufacturing a field effect transistor, method for manufacturing a volatile semiconductor memory element, method for manufacturing a non-volatile semiconductor memory element, method for manufacturing a display element, method for manufacturing an image display device, and method for manufacturing a system
US10818705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2017 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Nov 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0264
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a field effect transistor including a gate-insulating layer, an active layer, and a passivation layer. The method includes a first process of forming the gate-insulating layer; and a second process of forming the passivation layer. At least one of the first process and the second process includes: forming a first oxide containing an alkaline earth metal and at least one of gallium, scandium, yttrium, and a lanthanoid; and etching the first oxide by use of a first solution containing at least one of hydrochloric, acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide water.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.