III-V semiconductor device with integrated protection functions
US10818786B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | May 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/411
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
We disclose a III-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first gate terminal formed over the first III-nitride semiconductor region between the first terminal and the second terminal. The device also includes a second heterojunction transistor formed on a substrate, the second heterojunction transistor comprising: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a third terminal operatively connected to the second III-nit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.