Gate voltage plateau completion circuit for DC/DC switching converters
US10819237B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | May 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M1/0202
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.