Level shifter circuit with self-gated transition amplifier
US10819319B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 20, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Nov 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter circuit configured to convert a digital input signal with a first high logic level to a digital output signal having a second high logic level substantially higher than the first high logic level is provided. The level shifter circuit may include a PMOS latch circuit configured to receive the digital input signal and having first and second latch outputs and a current mirror circuit having a mirror input and a mirror output. The mirror input may be at least partly gated by a switch having a control input. The mirror output may be coupled to the first latch output. The control input may be coupled to the first or second latch outputs, and the digital output signal is provided from the first and/or second latch outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.