Self-regulating body-biasing techniques for process, voltage, and temperature (PVT) fluctuation compensation in fully-depleted silicon-on-insulator (FDSOI) semiconductors
US10819331B1 · kind B1 · utility
1Cited by
3References
20Claims
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Key dates
| Filing date | May 7, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | May 7, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Self-regulating body-biasing techniques for Process, Voltage, and Temperature (PVT) fluctuation compensation in Fully-Depleted Silicon-on-Insulator (FDSOI) semiconductors are disclosed. In an illustrative, non-limiting embodiment, an electronic device may include a logic cell having a plurality of FDSOI transistors manufactured thereon; and at least one current source coupled to a body terminal of each transistor in a subset of the FDSOI transistors, wherein the current source is configured to output a high-impedance current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.