Reset isolation for an embedded safety island in a system on a chip
US10819334B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Apr 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.