Bias circuit for use with divided bit lines
US10819936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Feb 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/79
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.