Test architecture for light emitting diode arrays
US10820397B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Nov 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B47/18
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods are presented relating to a plurality of current sources for generating a plurality of first bias currents to drive a plurality of LEDs and a plurality of measurement circuits for obtaining a plurality of first voltage measurements for the LEDs during a first test cycle. The current sources are further configurable to generate a plurality of second bias currents for driving the LEDs, and the measurement circuits are further configurable to obtain a plurality of second voltage measurements for the plurality of LEDs, during a second test cycle. A memory device is configured to store the first and second bias currents and first and second voltage measurements as a current-voltage (I-V) performance characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.