Multi-layer circuit board and electronic assembly having same
US10820408B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Feb 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09618
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-layer circuit board comprising a carrier plate with an upper surface and a lower surface, and at least one electrically conductive upper inner layer located on the upper surface of the carrier plate and an electrically insulating upper intermediate layer located thereon, and an electrically conductive upper outer layer located thereon, forming the outermost layer of the upper surface. At least one electrically conductive lower inner layer is located on the lower surface of the carrier plate and an electrically insulating lower intermediate layer located thereon, and an electrically conductive lower outer layer located thereon, forming the outermost layer of the lower surface. The upper and/or lower outer layers are populated with components, and conductor paths in one of the inner layers are oriented in different directions from conductor paths in the other inner layer, and the region between the conductor paths is flooded with a voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.