Systems and methods for implementing random access memory in a flow-based machine perception and dense algorithm integrated circuit based on computing and coalescing of indices
US10824370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2020 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for random access augmented flow-based processing within an integrated circuit includes computing, by a plurality of distinct processing cores, a plurality of linear indices and associated valid bits; propagating the plurality of linear indices in a predetermined manner to a plurality of columns of first-in, first-out buffers; loading, from the FIFO buffers, the plurality of linear indices to a content addressable memory; at the CAM: coalescing redundant linear indices in each of the plurality of FIFO buffers; performing lookups for a plurality of memory addresses based on the plurality of linear indices; collecting at a read data buffer a plurality of distinct pieces of data from one of an on-chip memory based on the plurality of memory addresses; reading the plurality of distinct pieces of data from the read data buffer; and propagating the plurality of distinct pieces of data into the processing cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.