Generating and verifying hardware instruction traces including memory data contents
US10824426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Apr 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.