Memory system architectures using a separate system control path or channel for processing error information
US10824499B2 · kind B2 · utility
8Cited by
42References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2018 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Feb 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.