Scalable neuromorphic core with shared synaptic memory and variable precision synaptic memory
US10824937B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2016 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Aug 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/049
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic neuromorphic core processor circuit and related method include a processor, an electronic memory, and a dendrite circuit comprising an input circuit that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map table provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit comprises a routing list that is a set of synaptic connections related to the set of dendrite compartments, each being n-tuple information comprising a dendriteID and a weight stored in the memory. The synapse configuration circuit associates the identifier with the set of synaptic connections, a dendrite accumulator comprising a weighting array. It accumulates weight values within a dendritic compartment identified by the dendriteID and based on the n-tuple information associated with the set of synaptic connections associated with the identifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.