Bit line structure for two-transistor static random access memory
US10825508B1 · kind B1 · utility
3Cited by
6References
8Claims
0Family size
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Key dates
| Filing date | Dec 12, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Dec 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit line structure for two-transistor static random access memory (2T SRAM), including multiple bit lines extending over multiple 2T SRAMs in a first direction, wherein each bit line consists of multiple first portions and second portions extending in the first direction and electrically connecting with each other in an alternating manner, and the first portions and the second portions are in a first dielectric layer and a second dielectric layer respectively, and the first portions of each bit line correspond to the second portions of adjacent bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.