Shift register unit, driving method thereof and gate driving circuit
US10825538B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 12, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Mar 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/02
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register unit, a driving method and a gate driving circuit are provided. The shift register unit includes a pull-up node control circuit, a pull-down node control circuit, a capacitor circuit, an output circuit and a noise reduction adjustment circuit. The noise reduction adjustment circuit is connected to a pull-down node and a first level input end, and configured to reduce an increasing rate of a potential at the pull-down node within a noise reduction time period of a maintenance phase, and reduce a decreasing rate of the potential at the pull-down node within a non-noise-reduction time period of the maintenance phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.