Method for making high voltage transistors insensitive to needle defects in shallow trench isolation
US10825717B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Jul 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for reducing transistor sensitivity to shallow trench isolation defects (STI) includes filling a trench formed in a substrate of a semiconductor device, at least partially, with a first oxide, the trench defines an STI and includes a defect extending from the substrate. A mask defines a planar area within the isolation region including a first lateral distance between an edge of the mask and an edge of the isolation region. The first oxide is at least partially removed beneath the planar area with an oxide etch to expose a top portion of the defect. The top portion of the defect is removed with a semiconductor etch. After removing the top portion of the defect, the trench is at least partially filled with a second oxide. A field plate of a split-gate transistor is formed over the STI.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.