Semiconductor package
US10825774B2 · kind B2 · utility
3Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | May 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.