Low power logic family
US10826498B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2020 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Feb 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor building block is disclosed which includes a plurality of logic gates, each having at least one P-channel device, at least one N-channel device, and a current controller controlling current for each of the plurality of logic gate having a voltage source input (vdd), a ground input (vss), a first input current (ibiasn) adapted to control current through the at least one N-channel device, a second input current (ibiasp) adapted to control current through the at least one P-channel device, and an analog voltage input (delta) representing i) a predetermined ratio between respective on currents in the at least one P-channel device to ibiasp, and ii) the predetermined ratio between respective on currents in the at least one N-channel device to ibiasn.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.