All digital phase locked loop (ADPLL) with frequency locked loop

US10826505B1 · kind B1 · utility

Assignee

• NXP B.V. · NL

Inventors

• Ulrich Moehlmann · Hamburg, DE
• Andreas Kollmann · Pfalzgrafenweiler, DE
• Christian Scherner · Hamburg, DE

Key dates

• Filing date: Jun 24, 2019
• Grant date: Nov 3, 2020
• Expiry date: Jun 24, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L2207/50
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A hardware device includes a frequency lock loop (FLL) that includes a phase loop filter, and a phase lock loop (PLL) such as an all digital PLL (ADPLL) that includes a frequency loop filter. A controller provides a first control signal to the FLL and a second control signal to the PLL when the device operates the same. The device can also include a digital controlled oscillator (DCO) and part of one or more of the FLL and the PLL. The FLL and the PLL include first and second filters, respectively. The filters are coupled to the DCO. A time-to-digital converter (TDC) and a divider receive an input from the DCO. The controller forms a first loop with the first filter, the TDC, and the divider, and the controller forms a second loop with the second filter, the TDC, and the divider.