System and method for removing error in a system having an analog-to-digital converter
US10826512B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Aug 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system includes a first sensed voltage generated as a product of the first voltage reference and an unknown scalar, a second sensed voltage generated as a product of the first voltage reference and a known scalar, and an amplifier having gain error that generates a second voltage reference (first voltage reference or scaled version thereof). An ADC uses the second voltage reference to generate first and second digital values, representing the first and second sensed voltages, that contain error caused by the second voltage reference gain error. A processor uses the known scalar and a ratio based on the first and second digital values to remove the error from the first digital value. The first sensed voltage may be generated by pumping a current into a variable resistance sensor (VRS) whose resistance varies with respect to a time-varying stimulus (e.g., temperature) and is proportional to the unknown scalar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.