Systems and methods for maximizing power efficiency of a digital power amplifier in a polar transmitter
US10826738B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Jan 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/541
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A polar transmitter including a digital power amplifier cell that includes a first circuit and an amplifier circuit. The first circuit is configured to receive a phase modulated carrier signal and to generate a PMOS control signal and an NMOS control signal such that the PMOS control signal and the NMOS control signal have different duty cycles. The amplifier circuit is configured to receive the PMOS control signal at a PMOS transistor and the NMOS control signal at an NMOS transistor. The first circuit is configured to align the PMOS control signal and the NMOS control signal with respect to one another such that a time that the NMOS transistor and the PMOS transistor of the amplifier circuit are simultaneously conducting is minimized. The amplifier circuit is configured to generate an amplified modulated carrier signal in response to the PMOS and NMOS control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.